1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a multi-chip package.
2. Description of the Related Art
Generally, a semiconductor device including a double data rate synchronous dynamic random access memory (DDR SDRAM) has developed to satisfy needs of consumers.
Recently, a multi-chip package as a package technology of a semiconductor device is introduced. The multi-chip package represents one chip having a plurality of semiconductor chips. The multi-chip package increases a memory capacity using a plurality of memory chips or improves a performance using a semiconductor chip having different functions.
For reference, the multi-chip package is classified to a single-layered multi-chip package and a multi-layered multi-chip package. The single-layered multi-chip package represents that a plurality of semiconductor chips are laterally arrayed on a plane. The multi-layered multi-chip package represents that a plurality of semiconductor chips are stacked.
FIG. 1 shows a diagram illustrating a conventional multi die package.
Referring to FIG. 1, the conventional multi die package 100 includes a plurality of semiconductor chips CP_1 to CP_N and a substrate 110. The plurality of semiconductor chips CP_1 to CP_N are vertically stacked. Each of the plurality of semiconductor chips CP_1 to CP_N is coupled to the substrate 110. A pad of each of the plurality of semiconductor chips CP_1 to CP_N is arrayed on an edge of each of the plurality of semiconductor chips CP_1 to CP_N. The substrate 110 is electrically coupled to the pad of each of the plurality of semiconductor chips CP_1 to CP_N using a Tire.
However, since the interconnection is arrayed along an edge of the plurality of semiconductor chips CP_1 to CP_N, an area of the plurality of semiconductor chips CP_1 to CP_N may be increased, and an interposer layer may be requested to be arrayed between the plurality of semiconductor chips CP_1 to CP_N. Thus, while the multi die package may have merits than the single-layered multi-chip package, it may have demerits in view of a footprint because a form factor is increased.
Moreover, although a gold wire is arrayed between pads to improve a quality of a signal transferred through a wire, because of a hetero junction, a transfer speed of data is lowered and a skew of a signal may occur in stacked dies. Thus, this concern may cause a power over-consumption and lower the reliability of a signal.